1. Field of the Invention
The present invention relates to a Multibit Non-volatile memory and method and especially to a flash memory and method such as a fast-programmable Flash EEPROM (Electrically Erasable Programmable Read-Only Memory) device relying on hot-electron injection for programming which is particularly suited for high density low-voltage low-power applications and employs only two polysilicon layers.
2. Description of Related Art
Most Flash memories use Channel Hot Electron Injection (CHEI) at the drain side of the memory cell or Fowler-Nordheim Tunnelling (FNT) for programming. On the one hand the CHEI mechanism provides a relatively high programming speed (˜10 μs) at the expense of a high power consumption (˜400 μA/bit) which limits the number of cells that can be programmed simultaneously (so-called page-mode programming) at the moment to a maximum of 8 bytes (Y. Miyawaki et al., IEEE J. Solid-State Circuits, vol.27, p.583, 1992. Furthermore, in order to allow a further scaling of the transistor dimensions towards 0.18 μm and below, supply voltage scaling from 3.3V towards 1.8V also becomes mandatory. This supply voltage scaling is known to degrade the CHEI efficiency—and hence the corresponding programming speed—considerably. Today, these memories already use a bitline charge pump to provide a 4-5V drain voltage to the cell during programming and erasing. The problem with this solution is two-fold:
Since the internally generated programming voltages are not scaled down with respect to the technology generation, it becomes practically impossible to further scale the cell itself, in terms of both vertical (i.e. dielectric thickness) and lateral (i.e. gate length) dimensions;
Due to the high power needed to trigger the CHEI it becomes harder and harder to generate these voltages on-chip from a high voltage generator or charge pumping circuit. Also, the relative area of the charge pumps and the corresponding high-voltage switching circuitry increases with respect to the useful area of the memory chip.
The Fowler Nordheim tunnelling (FNT) on the other hand provides slower programming times (˜100 μs) and a lower power consumption which allows larger pages (˜4 kbit) in order to reduce the effective programming time to 1 μs/byte (T. Tanaka et al., IEEE J. Solid-State Circuits, vol.29, p.1366, 1994). Further improvement is, however, limited by tunnel-oxide scaling limits and by the very high voltages (˜15V) needed on chip for FNT, both compromising device reliability and process scalability.
The recent success of Source-Side Injection (SSI) as a viable alternative for programming over FNT and CHEI for Flash programming, is mainly due to its unique combination of moderate-to-low power consumption with very high programming speed at moderate voltages. Source-Side Injection has very high efficiency in generating hot electrons in the channel. It also provides very high efficiency in collecting the channel hot electrons onto the floating gate. SSI programming improves reliability and allows for re-programming using on-chip charge pumps. A typical example of such a device relying on SSI for programming is the Applicant's High Injection Metal-Oxide-Semiconductor or HIMOS® (an IMEC registered trademark) memory cell (J. Van Houdt et al., 11th IEEE Non-volatile Semiconductor Memory Workshop, February 1991; J. Van Houdt et al., IEEE Trans. Electron Devices, vol.ED-40, p.2255, 1993). As also described in the U.S. Pat. Nos. 5,583,810 and 5,583,811, a speed-optimised implementation of the HIMOS® cell in a 0.7-μm CMOS technology exhibits a 400 nanoseconds programming time while consuming only a moderate current (˜35 μA/cell) from a 5V supply. This result is obtained when biasing the device at the maximum gate current, i.e. at a control-gate voltage (Vcg) of 1.5V. In terms of the feature size F (i.e. the smallest dimension on chip for a given technology), the HIMOS® cell area corresponds to ˜30F2. This is fairly large as compared to the high density Flash memory concepts which are all in the <10F2 range.
However, due to the growing demand for higher densities, also in embedded memory applications like e.g. smart-cards and embedded microcontrollers, a continuous increase in array density and the scaling of the supply voltage become mandatory. This evolution calls for more aggressive cell-area scaling and for low-voltage and low-power operation.
There have been many attempts to solve this problem by the fabrication of high-density high-performance Flash memory device using 3 polysilicon layers. However, the solutions found suffer from a number of significant disadvantages that will be discussed below in more detail.
U.S. Pat. No. 5,284,784 by Manley and U.S. Pat. No. 4,794,565 by Wu describe so-called “sidewall gate” devices. The floating gate FG is formed in the first polysilicon layer, while the select gate is formed by a polysilicon sidewall spacer. This spacer can be formed in the second polysilicon layer (Manley, FIG. 1) or in the third one (Wu, FIG. 2). The programming mechanism is source-side hot-electron injection. Next to the triple poly process, this solution has a lot of disadvantages:
The sidewall select gate is formed by depositing a polysilicon layer on the chip which is then partially removed selectively by using anisotropic (dry) techniques. It is, however, very difficult to control this selective etching operation, as for example the width of the spacer remaining after etching determines the effective channel length during programming and this parameter should be tightly controlled. Furthermore, the effective channel length is also influenced by the junction implant when going through the thinner portion of the spacer.
Since the select gate controls only a short portion of the channel, it is not straightforward to switch off the transistor channel in some cases, e.g. when reading/writing a particular cell the select gates of the (erased) cells sharing the same bitline have to be able to reduce their channel current to zero in order to prevent leakage currents and/or unwanted programming in the array. Usually, the thickness of the polysilicon, which determines the width of the spacer, is smaller than the minimum feature size, which compromises the hard-off situation, which is highly desired in a memory array.
It is well known that the efficiency of the SSI mechanism is closely linked to the thickness of the oxide spacing in between the select and the floating gate (see e.g. J. Van Houdt et al., IEEE Transactions on Electron Devices, vol.39, no.5, May 1992). By putting the sidewall select gate right next to the control gate (CG) (FIG. 2), this oxide spacing has to remain fairly thick since it also has to isolate the high control gate voltage during programming form this sidewall select gate. Therefore, the injection efficiency is compromised by isolation requirements.
The main problem with these devices, however, is the difficulty of contacting the cells in a large array of memory cells. Indeed, the sidewall gate is also used for wiring and this has a considerable negative impact on the parasitic resistance in a large memory array, as explained in U.S. Pat. No. 5,394,360, issued Feb. 28th, 1995, to T. Fukumoto (col.1 lines 37-41). Also, variations in sheet resistance, due to variations in spacer profile and/or doping, can lead to poor cell uniformity in large arrays which typically shows up as a severe manufacturability issue.
U.S. Pat. No. 5,338,952, issued Aug. 16th, 1994, to Y. Yamauchi, solves some of the problems mentioned above by forming the floating gate as a polysilicon sidewall spacer (FIG. 3). However, the major drawbacks of the sidewall gate device are still present in the memory cell described in this patent;
The sidewall gate is still formed by depositing a polysilicon layer on the chip which is then removed selectively by using anisotropic (dry) etching. In this case, the width of the spacer remaining after etching determines the effective channel length during read-out and this parameter should be tightly controlled. Indeed, if electrons are stored on the floating sidewall gate, the portion of the channel controlled by this sidewall has to be switched off efficiently, which is not trivial. As already mentioned above, the thickness of the polysilicon, which determines the width of the spacer, is usually smaller than the minimum feature size, which compromises the hard-off situation which is highly desired in a memory array. Eventually, the cell may exhibit a soft-on and a hard-on state instead of hard-off/hard-on states as required for fast access. Furthermore, since erasing is now to be achieved from the sidewall towards a sufficiently underdiffused drain junction, the effective channel controlled by the spacer is even smaller. This makes the leakage problem during read-out even more critical.
Since the floating gate is a sidewall spacer, the coupling ration between the control gate (3rd polysilicon layer) and this floating gate will be rather small. This increases the necessary program/erase voltages, which is typically 12V for programming and −11V for erasing as mentioned in the corresponding conference paper “A 5V-only virtual ground Flash cell with an auxiliary gate for high density and high speed applications” by Y. Yamauchi et al., IEDM Tech. Dig., p.319, 1991.
An alternative memory cell with 3 polysilicon layers, which also uses the source-side injection mechanism similar to the applicant's HIMOS® cell, is disclosed in U.S. Pat. No. 5,280,446. The major difference with the above discussed prior art is the absence of a sidewall gate. Instead, first and second polysilicon layers are etched in a stacked way and the select gate is added on top by a 3rd polysilicon layer. Also this method has some major disadvantages:
It is known to one skilled in the art that such a processing scheme introduces considerable complexity which makes it difficultto use in an embedded memory application.
On the other hand, the used erase voltage is still −12V provided that the bitline is biased at 5V. In future generations, when the supply voltage and hence also the bitline voltage go down, aggressive tunnel oxide scaling will be required in order not to have an increase in this negative voltage.
The oxide spacing between the select gate and the control gate has to be kept quite thick because this oxide also serves to isolate the high programming voltage from the select gate in order not to have a soft-erase effect or even oxide breakdown during programming. This restriction compromises scaling—in general—and also—more in particular—decreases the injection efficiency which is directly linked to the thickness of this spacing as explained extensively by J. Van Houdt et al. in IEEE Transactions on Electron Devices, vol.39, no.5, May 1992.
In the European patent application EP 008702458, filed Oct. 25, 2000, a double polysilicon memory cell structure is described. This cell structure still enables to obtain a high performance by the introduction of a novel programming scheme (Drain Enchanced Secondary Injection or DESI). This application shows a compact cell (about 15F2) which, however, still suffers from the basic drawbacks of the split-gate structure:
The split gate structure suffers from an inherent misalignment problem, since the second poly (control gate) is always slightly misaligned with respect to the first poly (floating gate). This misalignment does not scale proportionally to the feature size of the technology, and, therefore, introduces larger non-uniformities in programming behaviour and in read current when scaling down. In the case pending European patent application EP 1096572 A1 claiming priority of U.S. pending patent application Ser. No. 09/696,616 also the gate coupling ratio is subject to a misalignment error further increasing the spread on device characteristics. This latter sensitivity can be solved by completely encapsulating the floating gate by the control gate but this is at the expense of cell area and reliability since then the oxide between wordline and bitline needs to withstand the stress of both gate and drain voltages during program/erase conditions.
A second major scaling problem is the requirement of having a separate self-aligned drain junction: the mask for this implant should cover part of the floating gate to make sure that the implant is only present in a self-aligned way at the drain end of the channel and not at the source side of the floating gate.
For example, in 0.18 μm technology, drawing both channels at 0.18 μm dimensions could be marginal if misalignments are not well controlled to values well below 70 nm (3*standard deviation), and even then, the current drawn from the cell would vary by more than a factor of two from lot to lot. Starting from 0.13 μm technology, it becomes clear that both channels will need to remain longer than the feature size which implies not scaling the lateral dimensions any further.
As explained above, poly spacer technology, as a self-aligned process, has been extensively tried out in order to circumvent these problems, however, without any commercial success so far.
Another solution to obtain self-aligned structures is the so-called dual bit approach, which is described in U.S. Pat. No. 5,278,439, issued on Jan. 11, 1994 to Y. Y. Ma et al. in which the device is a triple poly floating gate version and in the paper “Twin MONOS cell with dual control gates” by Hayashi et al. (Halo and New Halo), presented at the 2000 VLSI Technology Symposium, which describes a nitride charge trapping version. However, both structures suffer from major drawbacks:
When using a triple poly layer approach (U.S. Pat. No. 5,278,439), the device suffers from the same drawbacks as the related U.S. Pat. No. 5,280,446, which has already been discussed above. Only the misalignment issue is resolved at the expense of very complicated processing.
When using a poly spacer technology as in the Halo device, the device suffers from all major problems related to poly spacers as discussed above (U.S. Pat. No. 5,338,952). Some additional drawbacks of such a spacer technology are for example poor interconnect properties causing yield and manufacturability problems (spacer uniformity in terms of shape, width, thickness, doping, . . . ) and variations in the effective channel length beneath the spacer because of the drain junction implant going through the thinner portion of the spacer. This will affect the device performance considerably unless the thickness of the polysilicon layer is constant over the entire channel area. Also, the spacer is only 80 nm wide in a 0.25 μm technology and can, therefore, not easily be controlled. Finally, the spacer process puts a lower limit on the 1st poly thickness, because the spacer width is related to this parameter. This is an additional boundary condition for the cell geometry.
Moreover, in the Halo case, the wordline is used to form the spacers which implies that a contact is required either on both source and drain, or, alternatively, on every control gate, in order to have a wordline perpendicular to the bitlines of the memory array. This considerably increases the real bit size when implemented in a true memory array. Considering that the minimum size for a single cell as mentioned in the paper is already 3F2, this cell is considerably larger than the one of the present invention. The problem can be resolved by routing the 2nd layer of polysilicon over the spacers in horizontal direction (see U.S. patent application Ser. No. 20020005545, F. Widdershoven and J. Schmitz). The problem with this configuration is that the spacing between both spacers then needs to be defined from an additional sacrificial layer. Removal of this layer after spacer formation will inevitably attack an oxide-nitride-oxide or ONO layer under the poly spacers exactly at the source-side injection point. This is detrimental for device performance and reliability. Alternatively, a triple poly process could also fulfill the same array connectivity requirements (see U.S. Pat. No. 6,366,500 issued Apr. 2nd2002 by Ogura et al.), however at the expense of a complicated and therefore expensive process.
With respect to the previously discussed prior art, as far as it is known, neither poly spacer technologies, nor the dual bit triple poly layer approach mentioned above, have made it into production because of major manufacturability and yield problems, related either to the spacer itself, and/or to the third poly layer.